Referring to FIG. 1, a known III-nitride power semiconductor device includes III-nitride multilayer body 21 formed on a substrate 20. Substrate 20 is preferably formed of silicon, but may be formed of SiC, Sapphire or a III-nitride semiconductor such as GaN. Multilayer body 21 includes a III-nitride active heterojunction 21A. Active heterojunction 21A includes III-nitride barrier layer 21B (e.g. AlGaN) formed on a III-nitride channel layer 21C (e.g. GaN). As is well known, the thickness and composition of barrier layer 21B and channel layer 21C are selected so that a two-dimensional electron gas (2DEG) is formed in channel layer 21C close to the heterojunction of layer 21B and layer 21C. The current in the device is conducted through the 2DEG. Note that III-nitride multilayer 21 may include a III-nitride transition layer (e.g. formed with AlN), and a III-nitride buffer layer (e.g. GaN layer) disposed between substrate 20 and heterojunction 21A, when for example, substrate 20 is non-native (i.e. is not from the III-nitride semiconductor system) to the III-nitride system. For example, when silicon is used as a substrate material.
A device as described above further includes a first power electrode 30 (e.g. source electrode) coupled ohmically to heterojunction 21B and second power electrode 30′ (e.g. drain electrode) coupled ohmically to heterojunction 21A whereby current may be conducted between electrode 30, 30′ through the 2DEG. A gate dielectric body 27 is disposed over heterojunction 21A through which gate conductive body 35 can be capacitively coupled to the 2DEG in order to interrupt (depletion mode) or restore (enhancement mode) the same depending on the type of device.
The device further includes field dielectric bodies 25. Each field dielectric is disposed between a power electrode 30, 30′ and gate conductive body 35. As illustrated field dielectric body 25 is thicker than gate dielectric 27. Gate conductive body 35 extends over a field dielectric body 25. Note that each electrode 30, 30′ also rises along adjacently disposed field dielectric bodies 25 and over a portion thereof.
In the device shown by FIG. 1, overlap of the gate metal (a) over dielectric 25 contributes to gate to drain charge (Qgd). The overlap (b) of the ohmic electrodes 30 over dielectric 25 increases pitch size.
In a III-nitride device according to the present invention, either the overlap of gate metal or the overlap of ohmic metal over the field dielectric bodies, or both, are eliminated through, for example, a chemical mechanical polishing (CMP) step. As a result, QGD of the device may be improved, and also the cell pitch of the device may be improved.